This application relates to a ring oscillator structures, and more specifically to ring oscillators having controllable gain and output frequencies.
Low-complexity large-tuning range ring oscillators generally have high frequency gain. The availability of a high frequency clock having low jitter is of fundamental importance for the operation of integrated circuits containing building blocks like Analog to Digital Converters, Digital to Analog converters, Serial Interfaces, and wireless or wireline transceivers. A well known solution for the generation of high frequency clocks is the use of a Phase Locked Loop (PLL) circuit, that locks the frequency of a high-frequency oscillator (called a Controlled Oscillator, or “CO”) to a multiple (integer or non-integer) of a reference frequency. The frequency of a CO is tuned using a tuning signal.
A large number of applications require the high-frequency clock to be tunable over a broad frequency range, which could span, for instance, from a few hundred MHz to 10 GHz. Since the PLL might be included in big digital cores, or placed near building blocks which generate disturbances on a power supply, it is important that the CO has low frequency gain (Kco). The frequency gain is defined as ΔF/Δc, where Δc is the variation of the tuning signal and ΔF is the corresponding change in output frequency. Indeed the lower the Kco, the smaller the effect of disturbances or noise on the tuning signal or on the jitter of the clock output.
In many applications, it is customary to use a ring oscillator as the CO. The structure of a ring oscillator is basically a chain of delay cells where the output is fed back to the input. If the Barkhausen criterion is satisfied, this structure will oscillate, generating a clock signal. The frequency can be tuned by changing the delay of each delay cell by using either analog or digital tuning signals.